The key to the 20x breakthrough in effective area achieved by LOFT resides in the synergy between technologies imported from other fields of scientific research, both ground and space-based.
The crucial characteristic of the LOFT Large Area Detector is a mass per unit surface in the range of ~10 kg/m2 (for comparison, the largest predecessor, the RXTE/PCA, has >100 kg/m2), enabling ~20 m2 geometric area payload at reasonable weight. The ingredients for a sensitive but light experiment are the large-area Silicon Drift Detectors (SDDs) designed on the heritage of the ALICE experiment at CERN/LHC, and a collimator based on lead-glass microcapillary plates (the mechanical structure of the well-known microchannel plate). A properly developed ASIC is planned to be used to read out the large number of channels of the LOFT SDDs.



The primary enabling technology for the LAD is the large-area Silicon Drift Detectors (SDDs) developed for the Inner Tracking System (ITS) in the ALICE experiment of the Large Hadron Collider (LHC) at CERN, by one of the scientific institutes in the LOFT Consortium (i.e. INFN Trieste, Italy) in co-operation with Canberra Inc. The key properties of the Si drift detectors are their capability to read-out a large photon collecting area with a small set of low-capacitance (thus low-noise) anodes and their very small weight (~1 kg m-2). The conceptual structure of the large-area SDD and their working principle is shown in the figures below: the cloud of electrons generated by the interaction of an X-ray photon is drifted towards the read-out anodes, driven by a constant electric field sustained by a progressively decreasing negative voltage applied to a series of cathodes, down to the anodes at ~0 V. The diffusion in Si causes the electron cloud to expand by a factor depending on the square root of the drift time. The charge distribution over the collecting anodes then depends on the absorption point in the detector.

The electrical structure and working principle of an SDD used for the instruments on-board LOFT.
Size and functional drawing of a single SDD.
Energy spectra measured using a spare ALICE detector equipped with discrete read-out electronics, at room temperature. The FWHM energy resolution was measured as ~300 eV at 5.9 keV.
Example of performance (energy spectrum of single events for LAD) of the current SDD prototypes, using a Fe55 source (5.9 and 6.4 keV lines) at different temperatures. From top left to bottom right: -27°C, -4°C, +11°C, +24°C. The dominant effect here is the relative decrease in detector leakage current (absolute value of resolution not representative, due to higher intrinsic leakage current of this prototype).



Due to the high density and large number of SDD anodes, the front-end read-out of the LAD and WFM detectors is planned to be carried using ASIC (application specific integrated circuit) technology. As the LAD and WFM uses the same detector type, the ASIC design is based on the same requirements, with the only differences being related to the different anode pitch (the LAD is larger to optimize the power consumption, while the WFM is smaller for imaging purpose). The ASIC specifications are generally rather standard, with the tighter constraint deriving from the combination of low-noise and low-power, on a mixed-signal ASIC. The ASIC is implemented using TSMC MS/RF 0.18 µm CMOS technology, and is being developed under CNES funded by IRAP/LAB/CNES, with Dolphin Integration as the industrial partner. The design was optimized to operate at low temperatures (-20°C/-40°C), as required by the LAD and WFM detectors.

Simulations of the ASIC anticipate the achievement of the required LAD noise level (20 e-rms, EoL) within the required power consumption rate (0.6 mW/channel @ -20°C), as  for both LAD and WFM detector specifications.

Example of the ASIC+FEE+SDD for the LAD (here FEE stands for Front End electronics). The FEE is in green, 14 ASICs are placed in two rows at the edge of the FEE, and the SDD (yellow) is on the back of the FEE.
A picture of the ASIC test card realized at IRAP.
Layout photo of the 1st ASIC prototype, currently under testing. The 4 LAD processing channels (with larger pitch) are visible on the top left, the 4 WFM channels on the bottom left (fine pitch channels).


The other key element of the LOFT payload innovative design is the capillary-plate X-ray collimator. This is based on the technology of micro-channel plates (MCPs). A multi-pore, ~mm thin sheet of lead-glass is able to absorb soft X-rays coming from outside its aperture holes. The channel size is about ~20-30 µm, while the walls are as thin as ~4-6 µm. The available Lead content varies in the range ~38-55%. The aspect ratio of the holes ranges typically between ~40 and ~200 (thickness ~few mm) and the open area ratio ranges from 50% to 80%. These devices provide an effective shielding from photons arriving from outside the field of view up to ~40 keV, above the primary energy range of LOFT (2-30 keV). Photons with high energy passing through will be detected with low efficiency by the thin Si detector and will be  anyway discriminated by their energy deposition the detector.
Scanning electron microscope image of a sample LAD collimator.
Properties of the LOFT LAD collimator at different energies.